(1) Field of the Invention
The present invention relates to the field of computer architecture. More particularly, the present invention relates to signal communications within a computer system with particular emphasis on the use of buses for the exchanging of information between computer components.
(2) Art Background
Modern computer architectures place heavy emphasis on the use of buses for the exchanging of information between components of computer systems. A bus is a collection of common wires or signal lines to which a plurality of components may be coupled for exchanging information with one another. Often, peripheral and other devices are coupled to an input/output (I/O) bus such as the well-known EISA bus for shared communication by peripheral devices to the system's processing unit. Such peripherals may be external to the computer system or housed in an integral unit with the computer system but separate from the integrated circuit or circuits comprising the system's processing unit.
Another bus frequently found in modern computer architectures is the high speed memory bus. Such a bus is frequently used to provide communications between a processing unit, memory modules and other modules which benefit from much higher speed communication with the processing unit than that provided by a standard I/O bus. Other modules which might advantageously reside on the memory bus rather than the I/O bus include such things as video processing modules which require high data exchange rates and computation power from the system processing unit.
When a processing unit requires the services of another module situated on the memory bus, the processing unit will signal the address of the desired memory bus module which will acknowledge the address and respond accordingly. Traditionally this procedure may be carried out in two distinct manners. One is by using a centralized decoding mechanism. In this approach, a decoding module resides on the memory bus. Addresses propagated by the processing unit are decoded by the centralized decoder which then selects the appropriate resource on the memory bus for communication with the processor. During system initialization, the decoder's logic determines which resources correspond to which addresses. The advantage of this approach is that resources on the memory bus need not be provided with decoding logic in order to watch for addresses being propagated by the processing unit. In such a mechanism, the decoding module controls the direction of signal propagation over the select lines to the memory bus resources. The disadvantage of such a scheme is that it is not easily extensible for building modular systems. If the system needs to be expanded, the decoder must be redesigned.
An alternative mechanism to the one described above is to use a distributed decoding scheme. In a distributed decoding scheme, each resource or module on the memory bus monitors the bus for addresses being propagated by the processing unit. When an address is propagated on the memory bus by the processing unit, each resource or module, through its own decoding logic, determines if it is the resource being addressed by the processor. If a given resource is the target resource then that module controls the activation of its own select lines for communication to the processor. Obviously, a disadvantage to such a mechanism is that the modules on the memory bus must each be incorporated with decoding logic for responding to addresses propagated by the processing unit. This mechanism, however, does allow for much more modular systems where additional resources may be plugged into a memory bus without having to modify a centralized decoder.
It would be an advantage, and is, therefore, an object of the present invention to be able to incorporate favorable aspects of both types of address decoding means for use on a high speed memory bus without having to increase the number of signal lines for communication between a processor and modules on the high speed memory bus.
Another disadvantage to current computer architectures is that I/O address space is generally reserved for specific slots or locations on the system I/O bus. Often times, this I/O space goes unused. Because the I/O address space is limited, locking up unused space prevents placing high performance I/O devices on the memory bus. It would be a great advantage and is, therefore, another object of the present invention to provide for the reassignment of I/O space originally dedicated for use by I/O devices on the I/O bus to be selectively provided to resources on the memory bus during system initialization to eliminate the problems described above.